Which of the following memory attributes, specified in a translation table entry, could be used to protect a page containing a read-sensitive peripheral from speculative instruction fetches?

A. S (Secure)

B. nG (non-Global)

C. xN (Execute Never)

D. AP (Access Permission)

A Just-In-Time compiler writes instructions to a region of memory that is configured using a writeback cache strategy. For the locations that have been written, what is the MINIMUM cache maintenance that MUST be performed before the new instructions can be reliably executed?

A. Instruction cache clean only

B. Instruction cache invalidate only

C. Data cache clean and instruction cache invalidate

D. Data cache invalidate and instruction cache invalidate

In the ARM instruction set what is the maximum branch distance for a Branch or Branch and Link instruction?

A. ±32MB

B. ±4MB

C. ±12KB

D. ±4KB

Which of the following ARM processors has the best energy efficiency (measured in mW/MHz)?

A. Cortex-M0+

B. Cortex-M4

C. Cortex-R4

D. Cortex-A15

If a Generic Interrupt Controller (GIC) implements 64 priority levels, which priority field bits hold the priority value?

A. bits [5:0]

B. bits [7:2]

C. bits [15:10]

D. bits [31:26]

In a symmetric multi-processing (SMP) software architecture, which of the following pairs of statements are TRUE? (Select the option in which BOTH statements are TRUE).

A. The roles of individual cores are determined dynamically. Each core has its own set of external peripherals.

B. Each core has the same view of memory and shared peripherals. Any user application, process or task can be scheduled to run on any core.

C. The roles of individual cores are statically determined by the system designer. Hardware must be implemented to provide cache coherency between the cores.

D. Each core has the same view of memory and peripherals. The roles of individual cores are statically determined by the system designer.

Which one of the following features must any processor support to conform to the ARMv7-A architecture?

A. NEON (Advanced SIMD)

B. Thumb-2 technology

C. TrustZone (Security Extensions)

D. Generic Interrupt Controller

Assuming a 4-core Cortex-A9 SMP system which does not use the Accelerator Coherency Port (ACP). and operates the L1 caches in writeback mode, in which of the following situations is a cache clean operation required?

A. An external DMA engine modifies data in a region of data memory which is already cached by the processor

B. An external agent needs to read data which has been modified by the processor in a cacheable memory region

C. Debugger reads data from a shared, cacheable memory location

D. One core modifies data in a shared cacheable memory region

Which events would be counted using the Performance Monitoring Unit (PMU) in order to measure the data cache efficiency of an application?

A. Memory read instructions, and memory write instructions

B. Architecturally executed instructions, and instruction fetches causing a cache line refill

C. Memory access instructions causing a cache line refill, and memory read and write operations causing a cache access

D. Memory read or write operations causing a cache access, and architecturally executed instructions

When using the ARM Compiler (armcc), which of the following possible keywords can be used to remove padding bytes from a structure?

A. __package

B. __packed

C. __compact

D. __compress